Electronic devices that populate the Internet of Things play increasingly important roles in our everyday lives. When these devices process, store or communicate personal or company-critical data, digital security becomes a necessity. However, mechanisms to secure electronic systems have a significant influence on the cost of the system and come with an overhead in energy consumption, computational delay and (silicon) chip area. Therefore, developing secure electronic systems is a balancing act between minimizing the overhead and maximizing the security. Moreover, in rapidly evolving markets, there is another parameter that can have a negative influence on the security strength of electronic devices, namely the time to market: it takes longer to bring a secure product to the market than to develop a product with no or little security measures in place.
In this project, we tackle the challenge of maximizing the security strength while minimizing the overhead w.r.t. energy consumption, computational delay and hardware resources as well as reducing the time to market of digital electronic systems. We specifically focus on the fast development of efficient cryptographic hardware with protection against physical attacks, i.e., attacks that exploit the physical implementation of cryptographic algorithms.
Physical attacks are categorized into:
- side-channel analysis attacks that target the extraction of secret information by monitoring side-channels like the power consumption, the electromagnetic emanation or the timing of the device, and
- fault analysis attacks that aim at introducing computational errors that lead to the leakage of secret information.
Physical security is of vital importance when potential attackers can easily get in the vicinity of an electronic system. This is the case in, e.g., medical sensor devices, wearables and implants, which are typically constrained in energy budget, cost and form factor, and are therefore the perfect use case for the results of the PROACT project.
As digital data are omnipresent in our daily lives, the need for digital security is growing rapidly. This is illustrated by popular media frequently reporting on attacks that expose the security flaws of real-life electronic systems. A very powerful type of attack is a physical attack, which exploits the physical implementation of a cryptographic algorithm, as shown in Fig. 1. The first category of physical attacks are side-channel analysis attacks, that analyze the information available through side-channels, such as the power consumption, the electromagnetic (EM) emanation or the timing behavior of an electronic system. Another type of physical attack is a fault analysis attack, which perturbates the system, e.g., through the injection of a laser beam, a clock glitch or a power supply glitch, in order to retrieve secret information. Especially for Internet-of-Things (IoT) devices, physical attacks form an underestimated threat and need to be dealt with through proper countermeasures. To achieve the highest level of physical security, protection mechanisms need to be foreseen throughout all steps in the knowledge value chain: in the design of cryptographic algorithms, in the design of cryptographic circuits, and in the physical implementation of cryptographic chips. Additionally, design choices made in one of these steps introduce constraints in other steps, such that interaction between the steps in the chain is indispensable.
✓ _PROACT covers the entire knowledge value chain in the development of physically secure cryptographic hardware, from algorithms to fabricated chips. Since many IoT devices are limited in energy/power consumption and computing resources, implementing countermeasures is a challenging task. Manual efforts by experienced designers can be effective, but are prone to errors and do not lead to optimal results when the design space is large. Existing design automation tools can optimize towards low energy/power and low resources, but do not take into account physical security.
✓ _PROACT develops design automation tools with low energy/power consumption, low computational resources and high physical security strength as optimization goals.
The IoT market consists of rapidly evolving applications. Therefore, minimizing the time to market of new products and services is crucial to survive for companies that operate in this market segment. However, evaluating the physical security of a cryptographic chip is typically something that is done after the (silicon) chip is fabricated. This makes the elapsed time between the design of a cryptographic algorithm/circuit and the physical security evaluation very long. A weakness detected in the evaluation phase, leads to a re-spin of the chip, taking away the competitive advantage of the company that intends to be the first to bring a new IoT application to the market.
✓ _PROACT designs, implements and validates a pre-silicon simulator for physical security to maximize the chances of first-time-right cryptographic chips.
We aim at answering the following research questions:
- What are the problems with respect to physical security in existing cryptographic algorithms and how can we design algorithms that are resilient against physical attacks?
- Which cryptographic circuits have optimal physical security strength, energy consumption, resource occupation and performance, or an optimal trade-off of these properties?
- How can we use design automation to improve the efficiency and the physical security of cryptographic circuits? - How can we design a pre-silicon physical security simulator with optimal accuracy and simulation speed?
- How can we use artificial intelligence to improve the accuracy and simulation speed of the pre-silicon simulator?
- Which state-of-the-art and beyond-state-of-the-art analysis methods can be used to perform a systematic evaluation of the developed cryptographic chips and validation of the pre-silicon simulator?
PROACT concentrates on the following scientific contributions:
- Novel cryptographic algorithms and circuits will be designed with inherent protection against physical attacks. Existing algorithmic design efforts mainly concentrate on maximizing the theoretical security strength and optimizing the efficiency. PROACT will evaluate the physical security of existing algorithms and concentrate on cryptographic algorithms with inherent resilience against physical security attacks. The design will be inspired by the ongoing NIST Lightweight Cryptography Standardization Competition and will contribute to the public evaluation phase the competition.
- Electronic design automation (EDA) tools for hardware design will be extended with physical security optimizations in the synthesis, placement and routing phase. Existing commercial electronic design automation tools for hardware design can optimize implementations with respect to power consumption, silicon area and operation speed, but have no built-in support for physical security. The PROACT project will make this possible by using methods that are compatible with existing commercial and academic design tools.
- A simulator will be developed for accurate pre-silicon physical security evaluations. Existing hardware simulators facilitate the accurate pre-silicon simulation of the functionality of a hardware circuit, but only allow the accurate simulation of physical side-channels on a very small scale. The reason is the enormous complexity of the required technology models for this kind of simulation. The PROACT project takes on this challenge using artificial intelligence techniques.
- Directives will be given to silicon technology providers with respect to benchmark circuits that they should fabricate. Regarding physical security, providers should measure and characterize their tech-nologies against physical side-channels. These measurements will then serve as the dataset that is used to train the simulator for a specific technology. While existing technology models can do an accurate pre-silicon simulation of the functionality and estimation of the energy consumption, the timing and the area, this is not yet the case for the physical security strength. The PROACT project will fill this gap.
The economic impact of these scientific contributions is two-fold:
- On the one hand, the cryptographic algorithms and circuits developed in PROACT will allow companies to bring products to the market with improved efficiency (lower energy consumption, higher performance and lower cost) and physical security.
- On the other hand, the design automation tools and the pre-silicon simulator developed in PROACT will allow companies to reduce the time to market of these products.
The PROACT consortium consists of two universities and one co-funding company: Leiden University (ULEI), Radboud University (RU), and Keysight. With Prof. Joan Daemen, Radboud University brings in expertise in symmetric-key cryptography and leakage-resilient cryptography. This is necessary for the project tasks related to the design and improvement of cryptographic algorithms. For the design and implementation of cryptographic circuits, the expertise of Prof. Nele Mentens of ULEI will be used. The knowledge on design automation comes from Dr. Todor Stefanov of ULEI. Prof. Lejla Batina and Dr. Ileana Buhan of Radboud University, together with Dr. Stjepan Picek will apply their knowledge on physical security and machine learning to develop the pre-silicon simulator. At Radboud University, the expertise of Prof. Patrick Schaumont (Worcester Polytechnic Institute, US) will also be used for the design of the simulator. He was a visiting professor at Radboud University in 2022-2023 as part of the Radboud Excellence Program.
PROACT also involves four national and two international cooperation partners: Signify, Synopsys, Neurasmus, Rambus, Nanyang Technological University (NTU, Singapore) and Cadence (UK). The first four cooperation partners are Dutch companies that are involved in the design and development of electronic products in different application domains. They will give input to the consortium on the specifications and requirements of products in these application domains, which can then be used for the benchmarking of the resulting chips with respect to physical security, energy consumption, cost and performance. They will also consider the project results and their applicability to their business.
